Integrated circuits are formed on semiconductor wafers, which are then sawed into semiconductor chips. The semiconductor chips may be bonded onto package substrates. During the bonding process, the solder regions between the semiconductor chips and the package substrates are reflowed. Conventional reflow methods include convection-type reflow and thermal compressive reflow. The convection-type reflow has relatively high throughput since a plurality of package substrates and the overlying dies may be bonded through the reflow at the same time. However, the convection-type reflow requires a long period of time to heat solder bumps. The resulting high thermal budget may cause significant warpage in semiconductor chips and the package substrates. As a result, cold joints may be resulted, and hence the semiconductor chips may have defective electrical connection to the corresponding package substrates. The solder regions may also have bridges. The delamination between low-k dielectric layers in the chips may also be resulted due to the stress as a result of the warpage.
The thermal compressive bonding requires a lower thermal budget than the convection-type reflow. However, the thermal compressive bonding has a very low throughput. During the thermal compressive bonding, a bond head picks up a chip, flips the chip, and attaches the chip to a package substrate. The bond head then goes through a temperature ramp-up process to heat the chip and the solder bumps that join the chip and the underlying package substrate. After the solder bumps are molten, the bond head goes through a cool-down process so that the solder bumps may solidify. This process is repeated for each of the chips, and hence the throughput of the thermal compressive bonding is very low, which sometimes may be only 1/15 of the throughput of the convection-type reflow.